(1) Field of the Invention
The present invention relates to a method for making recessed metal patterns in an insulator for metal plugs and interconnecting lines on integrated circuits using chemical/mechanical polishing (CMP), commonly referred to as the damascene process. More particularly, the invention uses a sacrificial thin organic layer to protect the underlying insulating surface from CMP-induced defects during polishing. Although the method is used to make metal plugs and lines, it is also applicable to the dual damascene process.
(2) Description of the Prior Art
The packing density of devices on integrated circuits has dramatically increased on ultra-large scale integrated (ULSI) circuits due to advances in semiconductor processing, such as the use of high-resolution photolithography and anisotropic plasma etching. In this sub-micron technology the allowed packing density of devices on an integrated circuit is strongly dependent on the metal interconnection density. As future design rules are more aggressively scaled down, for example, down to 0.18 to 0.1 micrometers (um), more levels of metal are required to effectively interconnect the high density of discrete devices on the chip.
However, as the number of metal levels increases and the topography gets rougher, it becomes increasingly difficult to pattern the metal levels. This results because a shallow depth of focus (DOF) is required when exposing the photoresist, and the rough topography can result in distorted photoresist images. Another problem is that it is difficult to etch sub-micron feature sizes in the metal layers using anisotropic etching without leaving residue in the underlying rough topography.
One method of circumventing these problems is to provide an insulator with a planar surface and to use a damascene process in which recesses are etched in the insulator and a metal is deposited and chem/mech polished back to provide metal interconnections in the recesses and resulting in a planar surface for the next level of processing. Unfortunately, the CMP results in polishing-induced defects, such as scratches that can adversely affect the reliability of the integrated circuit.
Several methods of making these recessed interconnections by chem/mech polishing are described in the literature. A general method of using low dielectric insulators for ULSI interconnections by a damascene process and a dual damascene process is described in the paper entitled "Low-k Dielectric Integration Cost Modelling," by Ed Korczynski in Solid State Technology, Oct. 1997, pages 123-128. Other methods for making planar metal/insulating structures are described. Fiordalice et al. in U.S. Pat. No. 5,578,523 describe a method using an aluminum nitride layer between a metal layer and an underlying dielectric layer to prevent dishing or cusping of the interconnection when the metal is polished back. Another method is described in U.S. Pat. No. 5,262,354 to Cote et al. in which a hard metal, such as tungsten, is formed over a low-resistivity soft metal to protect the soft metal from scratches and corrosion when the metals are polished back to form a planar surface. Gambino et al. in U.S. Pat. No. 5,573,633 teach a method for forming metal plugs in via holes in a planar insulating layer using a thick polysilicon layer as a chem/mech polish stop layer. A short chem/mech polish is then used to remove the polysilicon.
There is still a need in the semiconductor industry to provide a chem/mech polishing method that avoids scratches and other defects and corrosion of the underlying insulating layers when the metals are polished back to form plugs and metal interconnections recessed in the insulating layers such as by the damascene process.